Silicon on isulator (SOI) transistor and methods of fabrication

ABSTRACT

The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductordevices and more specifically to a silicon on insulator (SOI) transistorand methods of fabrication.

[0003] 2. Discussion of Related Art

[0004] In order to increase device performance, silicon on insulator(SOI) transistors have been proposed for the fabrication of modernintegrated circuits. FIG. 1 illustrates a standard partially depletedsilicon on insulator (SOI) transistor 100. SOI transistor 100 includes asingle crystalline silicon substrate 102 having an insulating layer 104,such as a buried oxide formed thereon. A single crystalline silicon filmbody 106 is formed on the insulating layer 104. A gate dielectric layer108 is formed on the single crystalline silicon body 106 and a gateelectrode 110 formed on the gate dielectric 108. Source and drainregions 112 and 114 are formed in silicon body 106 along laterallyopposite sides of gate electrode 110.

[0005] There are presently a couple different methods of forming SOIsubstrates where an single crystalline silicon body 106 is formed on aninsulating layer 104 which inturn is formed on a single crystallinesilicon substrate. In one method of forming a silicon on insulator (SOI)substrate, known as the SIMOX technique, oxygen atoms are implanted at ahigh dose into a single crystalline silicon substrate and annealed toform the buried oxide 104 within the substrate. The portion of thesingle crystalline silicon substrate above the buried oxide becomes thesilicon body. Another technique currently used to form SOI substrates isan epitaxial silicon film transferred technique. Another techniquecurrently used to form SOI substrates is generally referred to as bondedSOI. In this technique a first silicon wafer has a thin oxide grown onits surface that will later serve as the buried oxide in the SOIstructure. Next a high dose hydrogen implant is done to form a highstress region below the silicon wafer surface. This first wafer is thenflipped over and bonded to the surface of a second silicon wafer. Thefirst wafer is then cleaved along the high stress plane created by thehydrogen implant. This results in the SOI structure with a thin siliconlayer on top, buried oxide underneath, all on top of a single crystalsilicon substrate.

[0006] A problem with the bonded technique and the oxygen implanttechnique for forming SOI wafers or substrates, is that they cannot formthin, less than 10 nm, uniform epitaxial silicon body films. As such,the silicon body 106 of an SOI transistor formed with these techniqueshave thicknesses of greater than 100 nanometers. As such, when the SOItransistor is in operation and “turned ON” and the channel region 120 ofthe device inverts into the conductivity of the source/drain regions toform a conductive channel therebetween the inverted conductive channelregion 120 does not completely invert or deplete the entire thickness ofthe silicon body. As such, the SOI transistor is considered a partiallydepleted SOI transistor and not a fully depleted transistor. In order tofully deplete the silicon body, the silicon body film would need to beless than 30 nm. A fully depleted SOI transistor has better electricalperformance and characteristics than does a partially depleted SOItransistor. As such, present techniques are unable to fabricate fullydepleted SOI transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is an illustration of a cross-sectional view of a prior artpartially depleted silicon on insulator (SOI) transistor.

[0008]FIG. 2 is an illustration of an silicon on insulator (SOI)transistor in accordance with an embodiment of the present invention.

[0009] FIGS. 3A-3H illustrates a method of forming an SOI transistor inaccordance with an embodiment of the present invention.

[0010] FIGS. 4A-4F illustrates a method of forming an SOI transistor inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0011] The present invention is a novel silicon on insulator (SOI)transistor and its method of fabrication. In the following detaileddescription, numerous specific details are set forth in order to providea thorough understanding of the present invention. In other instances,well-known semiconductor processing techniques have not been describedin particular detail in order to not unnecessarily obscure the presentinvention.

[0012] The present invention is a novel SOI transistor and its method offabrication. The SOI transistor is fabricated utilizing the lateralcrystallization of a thin deposited amorphous or polycrystalline siliconor silicon alloy that contacts a single crystalline silicon substratethrough a small seed window in the insulating layer. The process of thepresent invention can be used to form very thin (less than 30nanometers) and uniform thickness single crystalline silicon films forthe body of the transistor enabling fully depleted SOI transistors to befabricated across a wafer. In an embodiment of the present invention, apolished stop layer along with a polishing planarization step are usedto precisely control the thickness and uniformity of the silicon orsilicon alloy body.

[0013] SOI Transistors

[0014] Shown in FIG. 2 is an SOI transistor 200 in accordance with anembodiment of the present invention. Transistor 200 includes a singlecrystalline silicon substrate 202. Single crystalline silicon substrate202 can include a top deposited silicon or silicon alloy epitaxial film.An insulating layer 204, such as silicon dioxide or silicon nitride, isformed on the single crystalline silicon substrate 202. A semiconductorbody film 206 is formed on the insulating layer 204. Semiconductor bodyfilm 206 can be a silicon film or a silicon alloy film, such as silicongermanium (Si_(x)Ge_(y)). A single crystalline window portion 208connects the silicon or silicon alloy body film 206 to the singlecrystalline silicon substrate 202 through a window or opening 207 formedin insulating layer 204. The silicon or silicon alloy body film includesat least a single crystalline silicon or silicon alloy portion 210 fromwhich the active channel region of the device is formed. The activechannel region 230 is formed by the lateral crystallization of anamorphous or polycrystalline silicon or silicon alloy film deposited onthe insulating layer 204 and on the single crystalline silicon substrate202 within the opening 207. A heating step causes crystallization of thebody film to start from the single silicon substrate 202 in the windowand laterally extend a length across insulating layer 204. The length ofcrystallization is on the order of 1.0 micron so that a device's activeor channel region 230 can be formed within the crystallization region.

[0015] A gate dielectric layer 214, such as silicon dioxide or siliconoxynitride, is formed on the single crystalline silicon or silicon alloybody portion 210. A gate electrode 216, such as a highly dopedpolycrystalline silicon gate electrode 216, is formed on the gatedielectric layer 214. A source region 218 and a drain region 220 areformed in the silicon or silicon alloy body film 206 on laterallyopposite sides of gate electrode 216. The source and drain regions havethe same doping concentration and conductivity type wherein the channelregion of the silicon body is of the opposite conductivity type and oflower doping. In an embodiment of the present invention, for a NMOSdevice the source and drain regions are of n type conductivity and havea doping density of between 10²⁰-10²¹ cm⁻³ while the channel region isof p type conductivity and has a doping density of between 10¹⁷-10¹⁹cm⁻³. For a PMOS device the source and drain regions have a p typeconductivity and a doping density of between 10²⁰-10²¹ cm⁻³ while thechannel region has a n type conductivity and a doping density of between10¹⁷-10¹⁹ cm⁻³.

[0016] In an embodiment of the present invention, the drain region 220has a single crystalline silicon or silicon alloy portion 224 formed bycrystallization and an amorphous or polycrystalline silicon portion 226which is not crystallized. In an embodiment of the present invention,the drain region is formed of only silicon crystalline silicon orsilicon alloy and does not include an amorphous or polycrystallinesilicon portion 226. The drain region 220 is completely isolated frommonocrystalline silicon substrate 202 by insulating layer 204.

[0017] The source region 218 is formed in single crystalline siliconbody portion 210. In an embodiment of the present invention, sourceregion 218 also includes single crystalline silicon window portion 208and a portion 228 of single crystalline silicon substrate 202. Directlyconnecting the silicon body layer 206 to the single crystalline siliconsubstrate 202 through seed window 207 provides a thermal heat sinkadvantage to the SOI transistor of the present invention. Alternatively,source region 218 can include only single crystalline silicon bodyportion 210 and be completely isolated by insulator 204 frommonocrystalline silicon substrate 202.

[0018] When the SOI transistor is turned “ON” a depletion region isformed in channel region 230 along with an inversion layer at thesurface of region 230. The inversion layer has the same conductivitytype as the source and drain regions and forms a conductive channelbetween the source 218 and drain 220 regions to allow current to flowthere between. The depletion region depletes free carriers from beneaththe inversion layer. This depletion region extends to the bottom ofregion 230, thus the SOI transistor can be said to be a fully depletedSOI transistor. Full depleted SOI transistors have improved electricalperformance characteristics over non-fully depleted, or partiallydepleted SOI transistors.

[0019] Methods of Fabrication of SOI Transistors

[0020] Fabrication of the SOI transistor in accordance with embodimentsof the present invention, will be described with respect to FIGS. 3A-3Hand FIGS. 4A-4F. In a method of forming a silicon on insulator (SOI)semiconductor device in accordance with an embodiment of the presentinvention, a single crystalline substrate 300, such as a singlecrystalline silicon substrate is provide as shown in FIG. 3A. In anembodiment of the present invention, the single crystalline siliconsubstrate 300 is doped with impurities to form a p type conductivitysubstrate with a doping concentration of between 10¹⁵-10¹⁸ cm⁻³.Monocrystalline silicon substrate 300 can include a top depositedepitaxial film, if desired. An insulating layer 302 is formed on singlecrystalline silicon substrate 300 as also shown in FIG. 3A. Insulatinglayer 302 is of a sufficient thickness and quality to isolate asubsequently formed semiconductor body from single crystalline substrate300. Insulating layer 302 can be any suitable insulating layer, such assilicon dioxide or silicon nitride. In an embodiment of the presentinvention, insulating layer 302 is an oxide film formed by thermaloxidation utilizing a wet ambient and is formed to a thickness ofapproximately 100 nanometers.

[0021] Next, as shown in FIG. 3B, a seed window or opening 304 is formedin insulating layer 302 to expose a portion of underlying singlecrystalline substrate 300. Opening 304 exposes a portion 306 of siliconsubstrate 300 which will be subsequently used as a seeding site fromwhich to laterally crystallize a subsequently formed silicon body layerfor the SOI transistor of the present invention. Opening 304 can be madeas small as the critical dimension or minimum of feature size of theprocess used to fabricate the transistor. In an embodiment of thepresent invention, the window has a width of approximately 60nanometers.

[0022] Next, as shown in FIG. 3C, a thin semiconductor body film 308 isformed on portion 306 of single crystalline silicon substrate 300 inwindow 304 and on insulating layer 302. Semiconductor body film 308 canbe an amorphous or polycrystalline silicon film or an amorphous orpolycrystalline silicon alloy film, such as silicon germanium. In anembodiment of the present invention, silicon body 308 is an amorphous orpolycrystalline silicon or silicon alloy film which is deposited in atwo step deposition process. The first deposition process is a selectivedeposition and as such, only deposits on silicon areas, such as siliconsubstrate region 306 in window 304, and not on insulating layer 302. Thesecond deposition step is a non-selective deposition which depositssilicon on the previously deposited silicon within window 304 as well ason insulating layer 302. The thickness of semiconductor body layer 308is chosen so that the entire channel region of a transistor formed onthe silicon body will fully deplete when the transistor is turned “ON”.In an embodiment of the present invention, silicon body layer 308 isformed to a thickness less than 30 nanometers and ideally to a thicknessof approximately 20 nanometers plus or minus two nanometers over theentire surface of a wafer.

[0023] Next, a dielectric capping layer 310 is formed on silicon bodyfilm 308 as shown in FIG. 3D. Dielectric capping layer 310 can be usedto keep the top surface of silicon body 308 smooth during the subsequentlateral crystallization step. Dielectric capping layer 310 can be anysuitable dielectric layer, such as silicon dioxide or silicon nitrideformed to a thickness of approximately 100 nm.

[0024] Next, silicon or silicon alloy body 310 is crystallized to form asingle crystalline silicon or silicon alloy film portion 314 as shown inFIG. 3E. A high temperature anneal can be used to laterally crystallizethe silicon body film 308. Crystallization begins at the silicon seedportion 307 and then grows laterally over insulating layer 302 as shownin FIG. 3E. The crystallization length 316 should be sufficiently longin order to provide a sufficient amount of single crystalline silicon orsilicon alloy film 314 for at least one transistors active channelregion. In an embodiment of the present invention, the crystallizationlength 316 is sufficiently long to provide single crystalline siliconfor multiple transistors. In an embodiment of the present invention, thecrystallization length is on the order of approximately 1.0 micron. Thecrystallization step need not crystallize the entire silicon or siliconbody 308 and can leave a portion 312 as amorphous or polycrystallinesilicon or silicon alloy, as shown in FIG. 3E. Ideally, thecrystallization anneal is accomplished with a method that provides athermal gradient which keeps the silicon seed portion 306 of substrate300 relatively cool while heating the silicon body 308. In this way, thecrystalline structure of the seed layer 306 remains aligned while thesilicon body layer heats up, melts and aligns to the crystallinestructure of the seed area 306 of single crystalline substrate 300. Inan embodiment of the present invention, a laser anneal process is usedto form single crystalline silicon or silicon alloy body portion 314. Inthe case of laser anneal, the wavelength of light chosen would be suchthat most of the radiant energy is absorbed in the silicon, or siliconalloy layer 308 and not in the dielectric layer or in the underlyingsilicon substrate 300. In an alternative embodiment of the presentinvention, a rapid thermal process (RTP) may be utilized. The annealtemperature time, and/or energy is utilized to control thecrystallization length 316 of silicon body portion 314. At this point, asingle crystalline silicon or silicon alloy film 314 has been formed onan insulating layer 302 enabling the subsequent formation of a siliconon insulator transistor. Well-known and standard process techniques cannow be used to complete the fabrication of a silicon on insulatortransistor.

[0025] For example, as shown in FIG. 3F, the dielectric capping layer310 is now removed from silicon body 308. At this time, well-knownion-implantation techniques can be used to dope silicon body 308 to ptype conductivity for n type devices and n type conductivity for p typedevices. Well-known masking and doping techniques, such asion-implantation or solid source diffusion may be utilized to dopesilicon body 308. Next, as also shown in FIG. 3F, silicon body 308 ispatterned with well-known photolithography and etching techniques toremove portions of silicon body 308 to form openings 318 in the siliconbody film in order to electrically isolate adjacent transistors. Next,as also shown in FIG. 3F, a gate dielectric layer 320, such as a silicondioxide or silicon oxynitride film, is grown on silicon body 308 withwell-known techniques. Next, a gate electrode material, such aspolycrystalline silicon, is deposited on the gate dielectric layer.Next, well-known photolithograph and etching techniques are utilized topattern the gate electrode material and gate dielectric layer into agate electrode 322 and gate dielectric 320 as shown in FIG. 3F. It is tobe appreciated that gate electrode 322 and gate dielectric 320 arepositioned over single crystalline silicon or silicon alloy portion 314of silicon body 308 as shown in FIG. 3F.

[0026] Next, a source region 326 and a drain region 324 are formed insilicon body 308 as shown in FIG. 3G. Source region 326 and drain region324 are formed along laterally opposite sidewalls of gate electrode 322defining a channel region 328 therebetween. Source region 326 and drainregion 324 are formed of n type conductivity for NMOS devices and a ptype conductivity for PMOS devices. Source region 326 and drain region324 can be formed with well-known techniques, such as ion-implantationor solid source diffusion. In an embodiment of the present invention,the source region and drain region are formed by ion-implantation. Thesource/drain doping step can be used to highly dope a polycrystallinegate electrode 322. In an embodiment of the present invention, the drainregion 324 formed and located so that it includes a portion of singlecrystalline silicon body 314 and a portion 312 of amorphous orpolycrystalline silicon body. Additionally, in an embodiment of thepresent invention, as shown in FIG. 3G, source region 326 is formed andlocated so that the source region includes single crystalline silicon orsilicon alloy 314 formed in window 304 of insulating layer 302 as wellas a portion of single crystalline silicon substrate 300. At this point,the fabrication of the silicon on insulator transistor of the presentinvention is complete.

[0027] Well-known semiconductor fabrication processes can now beutilized to interconnect the fabricated SOI transistor with othertransistors formed on substrate 300 to form an integrated circuit. Forexample, well-known interlayer dielectric fabrication techniques can beused to form an interlayer dielectric 330 and well-known contacttechniques can be utilized to form source, drain and gate contacts 332to enable electrical coupling by metallization layers 334 to otherdevices in the integrated circuit.

[0028] It is to be appreciated that the present invention utilizes alateral crystallization of a deposited amorphous or polycrystallinesilicon film to form a single crystalline silicon film on which the SOItransistor of the present invention is subsequently formed. Because thepresent invention relies upon the lateral crystallization, it isdesirable to keep the lateral crystallization length (i.e., distance thesingle crystalline silicon grows from the seed area over insulatinglayer 302 as shown in FIG. 3D) short as possible in order to insure aquality single crystalline silicon film. Accordingly, in an embodimentof the present invention, the crystallization length is kept to lessthan 10 microns and greater than 1 microns. It is to be appreciated thatbecause it is desirable to reduce the crystallization length, many(literally millions) of seed windows 304 would be formed in aninsulating layer 302 for each integrated circuit in order to provide asufficient amount of crystallized single crystalline silicon from whichto form the SOI transistors of the integrated circuit. In an embodimentof the present invention, there is between 1:1 to 1:10 ratiocrystallization seed windows to transistors. It is to be appreciatedthat the crystallization of the amorphous or polycrystalline siliconbody film 308 begins at the seeding cite 306 and grows in all directions(including into and out of the page in FIG. 3E). Additionally, it is tobe appreciated that windows 306 also extend into and out of the pagealong the gate width of the transistor. (As in typical convention, thegate length of a transistor refers to the dimension of the gateelectrode separating the source and drain regions as shown in FIGS.3A-3H while the gate width is the direction perpendicular thereto (i.e.,in a direction into and out of the page of FIGS. 3A-3H).)

[0029] Thus, accordingly the present invention forms multiple seedwindows 304 in insulating layer 302 to provide multiple seeding sitesfrom which a deposited amorphous or polycrystalline silicon film can becrystallized into single crystalline silicon for the various SOItransistors of an integrated circuit. In an embodiment of the presentinvention, sufficient seed windows are formed and located to insure thecomplete crystallization of the entire amorphous or polycrystallinesilicon film during the crystallization step. It is to be appreciated,however, that the entire amorphous or polycrystalline silicon film neednot necessarily be crystallized into single crystalline silicon and somecan remain as polycrystalline or amorphous silicon as long as thetransistor layout restrictions place the active channel regions overcrystallized silicon 314. If some of the silicon body remains asamorphous or polycrystalline silicon, the SOI transistors should belocated so that the amorphous or polycrystalline silicon film forms partof the drain region of the device as shown in FIG. 3H. Additionally,although the silicon body 308 is shown connected to the singlecrystalline silicon substrate 300 by the portion of silicon in window304, the silicon body need not necessarily be directly coupled to thesubstrate. For example, the transistors can be properly positioned sothat the silicon in or above window 304 can be etched away or isolatedfrom the silicon body during the silicon body etch step of FIG. 3F toprovide isolation between adjacent transistors.

[0030] In a method of forming an SOI transistor in accordance withanother embodiment of the present invention, as shown in FIGS. 4A-4F,the deposited silicon body is thinned by a polishing process and thethickness precisely controlled by the use of a thin polish stop layer.According to this embodiment of the present invention, a polish stopfilm 403 is conformally formed on insulating layer 302 formed on singlecrystalline silicon substrate 300 as shown in FIG. 4A. The polish stoplayer 403 is used to form a plurality of polish stops on insulatinglayer 302 for the subsequent polishing of the deposited silicon bodyfilm. As such, the polish stop film is formed of a material which can beselectively polished with respect to the subsequently formed siliconbody. (That is polish stop film 403 is formed of a material which can bepolished slower, preferably at least 5 times slower, than the siliconbody film.) In an embodiment of the present invention, the polish stopis a deposited silicon nitride, silicon oxide or silicon carbide film.The polish stop film 403 is deposited to the thickness desired of thesilicon body for the SOI transistor. In an embodiment of the presentinvention, the polish stop layer 403 is formed to a thickness of lessthan 40 nanometers and ideally to a thickness of less than or equal to20 nanometers so that a fully depleted SOI transistor can be formed.

[0031] Next, as shown in FIG. 4B, the polish stop layer 403 is patternedwith well-known photolithography and etching techniques to form aplurality of polish stop features 405 on insulating layer 302. Theregion 407 between polish stop features 405 are the location at which anSOI transistor or plurality of transistors are formed. As such, thespaces between features should be at least sufficient to accommodate atleast one SOI transistor. In an embodiment of the present invention,polish stop features 405 are separated by a distance of at least 1.0micron in order to provide sufficient area for the transistors length.

[0032] Next, as also shown in FIG. 4B, a silicon seed window 304 isformed through insulating layer 302 to expose a portion 306 of singlecrystalline substrate 300 as described above. Seed window 304 is formedwithin opening 407 between polish stop features 405.

[0033] Next, as shown in FIG. 4C, an amorphous or polycrystallinesilicon or silicon alloy body film 308 is blanket deposited onto polishstop features 405, onto insulating layer 302 within opening 407 and ontosingle crystalline silicon substrate portion 306 of substrate 300. Inthis embodiment of the present invention, the amorphous orpolycrystalline silicon body film can be deposited to a thicknessgreater than the thickness desired of the body layer for the fabricatedtransistor because it is to be subsequently polished back. It is thoughtthat by forming a thicker amorphous or polycrystalline silicon bodylayer 308 that the subsequent lateral crystallization anneal can obtainfurther lengths do to the increased thickness of the film. In anembodiment of the present invention, the amorphous or polycrystallinesilicon or silicon alloy film 308 is formed to a thickness greater then100 nanometers. Amorphous or polycrystalline silicon or silicon alloyfilm 308 can be formed with techniques as described above.

[0034] Next, a dielectric capping layer 310 is formed on amorphous orpolycrystalline silicon or silicon alloy layer 308 as described above.

[0035] Next, as shown in FIG. 4D, the amorphous or polycrystallinesilicon or silicon alloy film 308 is subjected to a high temperatureanneal to laterally crystallize the film 308 to form a singlecrystalline silicon or silicon alloy film 314 as described above. It isthought that by increasing the thickness of the silicon body film 308that the lateral crystallization length can be increased over what ispossible when a thin amorphous or polycrystalline silicon or siliconalloy body film is crystallized. A portion 312 of the amorphous orpolycrystalline silicon or silicon alloy body film 308 may remain asamorphous or polycrystalline silicon or silicon alloy as shown in FIG.4D.

[0036] Next, as shown in FIG. 4E, the dielectric capping layer isremoved with well-known techniques. The silicon body layer 308 is nowpolished back with well-known chemical mechanical polishing techniques.The silicon body layer 308 is polished down to the polish stop features405 as shown in FIG. 4E. The silicon body is polished with a polishingprocess and slurry which can selectively polish the silicon body film308 with respect to polish stop features 405. The polishing process iscontinued until all of the silicon body film 308 is removed from polishstop features 405 as shown in FIG. 4E. After the polishing process, thetop surface of silicon body 308 is substantially planar with the topsurface of the polish stop features 405 as shown in FIG. 4E. In thisembodiment of the present invention, there is no need to etch thesilicon body layer in order electrically isolated adjacent transistorsbecause the polish stop features 405 can be placed in appropriatelocations to provide such a function. By utilizing a polishing processand polish stop features 405, a silicon body 308 on which SOI transistorof the present invention is fabricated can formed to a precise anduniform thickness across the wafer and from wafer to wafer.

[0037] Next, as shown in FIG. 4F, a gate dielectric layer 320, a gateelectrode 322, a source region 326 and a drain region 324 are formed asdescribed above. This completes the fabrication of the SOI transistor inaccordance with an alternative embodiment of the present invention.

[0038] Thus, an SOI transistor and its methods of fabrication have beendescribed.

We claim:
 1. A semiconductor device comprising: a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon film having a single crystalline silicon or silicon alloy portion; a gate dielectric on said single crystalline silicon portion of said silicon film; a gate electrode on said gate dielectric; a source and a drain region formed on opposite sides of said gate electrode in said silicon or silicon alloy film; and a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon film.
 2. The semiconductor device of claim 1 wherein said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film has a thickness of less than 30 nanometers.
 3. The semiconductor device of claim 1 wherein said single crystalline silicon window portion forms part of said source region.
 4. The semiconductor device of claim 1 wherein said silicon or silicon alloy film further includes a polysilicon or an amorphous silicon or silicon alloy portion.
 5. The semiconductor device of claim 4 wherein said polysilicon or amorphous silicon or silicon alloy portion forms part of said drain region.
 6. A semiconductor device comprising: a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion having a thickness of less than or equal to 30 nanometers; a gate dielectric on said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film; a gate electrode on said gate dielectric; and a source region and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.
 7. The semiconductor device of claim 6 wherein in said silicon or silicon alloy film further comprises an amorphous or polycrystalline portion.
 8. The semiconductor device of claim 7 wherein said amorphous or polycrystalline portion forms part of said drain region.
 9. The semiconductor device of claim 7 further comprising a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film.
 10. The semiconductor device of claim 9 wherein said single crystalline silicon or silicon alloy window portion forms part of said source region.
 11. A semiconductor device comprising: a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion and an amorphous or polycrystalline portion; a gate dielectric on said single crystalline silicon or silicon alloy portion; a gate electrode on said gate dielectric; and a source and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.
 12. The semiconductor device of claim 6 further comprising a polish stop layer on said insulating layer adjacent to said silicon film.
 13. The semiconductor device of claim 11 wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide.
 14. A method of forming a semiconductor device comprising: forming an opening in an insulating layer formed on a single crystalline silicon substrate; forming an amorphous or polycrystalline silicon or silicon alloy layer in said opening on said single crystalline silicon substrate and on said insulating layer; and crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening and a least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer into a single crystalline silicon or silicon alloy film.
 15. The method of claim 14 further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and forming a gate electrode on said gate dielectric.
 16. The method of claim 14 wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 1.0 micron.
 17. The method of claim 14 further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.
 18. The method of claim 14 further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.
 19. The method of claim 18 wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.
 20. The method of claim 18 wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.
 21. The method of claim 14 wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness less than 30 nanometers.
 22. The method of claim 14 wherein said crystallization step comprises a laser anneal.
 23. The method of claim 14 wherein said crystallization step includes a high temperature anneal.
 24. A method of forming a semiconductor device comprising: forming a polish stop layer on a insulating layer formed on a single crystalline silicon substrate; forming an opening in said polish stop layer; forming an opening in said insulating layer within said opening in said polish stop layer; forming an amorphous or polycrystalline silicon or silicon alloy film in said opening on said single crystalline silicon substrate in said opening of said insulating layer, on said insulating layer within said opening in said polish stop layer, and on said polish stop layer; crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening in said insulating layer and at least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer within said polish stop layer into a single crystalline silicon or silicon alloy film; and polishing said single crystalline silicon or silicon alloy film on said insulating layer until said single crystalline silicon or silicon alloy film is removed from said polish stop layer and is substantially planar with said polish stop layer.
 25. The method of claim 24 further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and forming a gate electrode on said gate dielectric.
 26. The method of claim 24 wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 0.05 micron.
 27. The method of claim 24 further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.
 28. The method of claim 24 further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.
 29. The method of claim 28 wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.
 30. The method of claim 28 wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.
 31. The method of claim 24 wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness greater than >100 nanometers.
 32. The method of claim 24 wherein said crystallization step comprises a laser anneal.
 33. The method of claim 24 wherein said crystallization step includes a high temperature anneal.
 34. The method of claim 24 wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide or silicon oxide. 